Austria Mikro Systeme International AG
AS8201
TTP/C-C1 Communications
Controller
Data Sheet
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Key Features
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First dedicated controller supporting TTP/C (time triggered protocol class C)
Device for building up TTP/C nodes in a TTP/C local area networks (clusters).
Suited for dependable distributed real-time systems with guaranteed response time
application examples:
automotive: braking, steering, vehicle dynamics control, drive train control
industry: air plane flap control, rail way points
Bit data rate 2 Mbits/s @ clock 20 MHz, 5.0V
Fabricated in 0.6u CMOS process, automotive temperature range of -40 to 125deg C
1k x 16 RAM message, status and control area
RAM for instruction code and configuration data
16 bit non-multiplexed host CPU interface
16 bit RISC architecture
external firmware (FLASH memory) conforming the TTP/C specification
automatic booting after power on
software tools, design-in support, development boards available (
http://www.tttech.com)
120 pin PQFP Package
Description
The TTP/C-C1 communications controller is the first integrated device supporting serial
communication according to the TTP/C specification (time triggered protocol class C). It
performs all communications tasks such as reception and transmission of messages in a
TTP/C cluster without interaction of the host CPU.
TTP/C provides mechanisms that allow the deployment in high-dependability distributed real-
time systems. It provides the following services:
•
predictable transmission of messages with minimal jitter
•
fault-tolerant distributed clock synchronisation
•
consistent membership service with small delay
•
masking of single faults
Host
processor
Interface
RAM_DATA[15:0]
RAM_ADDRESS[10:0]
RAM_CEB
RAM_OEB
RAM_WEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
Receiver
Controller
network
interface
(CNI)
RXD[1:0]
TTP/C-C1
protocol
processor core
Bus
guardian
BDE[1:0]
XENA1
XIN1
XOUT1
TTP/C
bus -
Meadia
Drivers
Quarz or
Oscillator
MICROTICK
XENA0
XIN0
XOUT0
RESETB
Reset &
Time
base
Transmitter
TXD[1:0]
CTS[1:0]
OE[1:0]
Boot ROM
Interface
ROM_ADDRESS[16:0]
ROM_DATA[15:0]
ROM_RESETB
ROM_CEB
ROM_OEB
ROM_WEB
ROM_READY
Instruction
memory
Network
configuration
memory
(MEDL)
TEST_SE
Test
FTEST
Inter-
FTEST_IEN
face
LED[7:0]
Figure 1 Block Diagramm
Rev. NC, October 1999
Page 2 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
The CNI (controller network interface) forms a temporal firewall. It decouples the controller
network from the host subsystem by use of a dual ported RAM. This prevents the propagation
of control errors. The interface to the host CPU is implemented as 16 bit wide non-multiplexed
asynchronous bus interface.
TTP/C follows a conflict-free media access strategy called time-division-multiple access
(TDMA). This means, TTP/C deploys a time slot technique based on a global time which is
permanently synchronised. Each node is assigned a time slot in which it is allowed to perform
transmit operation. The sequence of time slots is called TDMA round, a set of TDMA rounds
forms a cluster cycle. After one cluster cycle the operation of the network repeats. The
sequence of interactions forming the cluster cycle is defined in a static time schedule, called
message-descriptor-list (MEDL). The definition of the MEDL in conjunction with the global time
determines the response time for a service request.
The membership of all nodes in the network is evaluated by the communication controller. This
information is presented in a consistent fashion to all correct cluster members. During
operation, the status of every other node is propagated within one TDMA round. The MEDL is
loaded into the configuration memory before run time when the system starts up.
Package and Pin Assignment
Type: PQFP 120, plastic quad flat package
TTP/C-C1
Communications
Controller
(TOP VIEW)
Figure 1 PQFP 120 pin package and pin assignment
Rev. NC, October 1999
Page 3 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
Pin Description
PinNr.
1
2
3-18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
VDD
VSS
RAM_DATA[0:15]
VDD
VSS
RAM_OEB
RAM_WEB
RAM_READYB
TIME_OVERFLOW
TIME_SIGNAL
TIME_TICK
MICROTICK
XENA0
VDD
VSS
XIN0
XOUT0
VSS
VDD
OE[0]
RXD[0]
TXD[0]
CTS[0]
BDE[0]
RESETB
Dir
P
P
I/O
P
P
I
I
O
O
O
O
O
I
P
P
A
A
P
P
I
I
PU
O
O
O
I
Description
positive power supply
negative power supply
DPRAM data bus, tristate
positive power supply
negative power supply
DPRAM output enable, active low
DPRAM write enable, active low
DPRAM ready, active low, indicates read/write operation finished
CNI control signal, overflow of global time
CNI control signal, CNI time signal
CNI clock signal, macrotick, typically about 1us at 20 MHz clock.
output of main clock, inverted to signal applied at pin XOUT0.
oscillator 0 (main clock) enable, active low.
positive power supply
negative power supply
analog pad from oscillator / use as input when providing external
clock
analog pad from oscillator / leave open when providing external
clock
positive power supply
negative power supply
channel [0]: transmitter output enable
channel [0]: receiver input
channel [0]: transmit data
channel [0]: transmitter clear to send
channel [0]: bus driver enable
(1) main reset input signal, active low. When connected the in-
ternal power-on reset function is overridden
(2) if unconnected: an internal reset is generated after power-on.
Reset pulse duration typically 24 us.
test input: scan enable, active high
test input: functional test mode, active high
test input: instruction insertion enable, active high
test outputs:
(1) in production test used as scan chain outputs
(2) in operation: can be used as generic output port, e.g. to drive
LEDs
channel [1]: transmitter output enable
channel [1]: receiver input
channel [1]: transmit data
channel [1]: transmitter clear to send
channel [1]: bus driver enable
oscillator 1 (bus guardian) enable, active low.
positive power supply
negative power supply
analog pad from oscillator / use as input when providing external
clock
analog pad from oscillator / leave open when providing external
clock
positive power supply
negative power supply
41
42
43
44-50
TEST_SE
FTEST
FTEST_IEN
LED[0:6]
I
PD
I
PD
I
PD
O
51
52
53
54
55
56
57
58
59
60
61
62
OE[1]
RXD[1]
TXD[1]
CTS[1]
BDE[1]
XENA1
VDD
VSS
XIN1
XOUT1
VSS
VDD
I
I
PU
O
O
O
I
P
P
A
A
P
P
Rev. NC, October 1999
Page 4 of 13
TTP/C-C1 Communications Controller Data Sheet
AS8201
Austria Mikro Systeme International AG
63-79
80
81
82
83
84
85
86
87-94
95
96
97-
104
105
106
107-
117
118
119
120
I
I
PU
I
PD
O
I/O
P
A
ROM_ADDRESS[0:16]
ROM_RESETB
ROM_CEB
ROM_OEB
ROM_WEB
ROM_READY
VDD
VSS
ROM_DATA[0:7]
VDD
VSS
ROM_DATA[8:15]
VDD
VSS
RAM_ADDRESS[0:10]
RAM_CEB
VDD
VSS
Input CMOS
Input CMOS with pull up
Input CMOS with pull down
Output CMOS
Input/Output CMOS tristate
Power Pin
Analog Pin
ROM address bus, range = 2^17 = 128k
ROM reset line, active low
ROM chip enable, active low
ROM output enable, active low
ROM write enable, active low; “
read” if high.
ROM ready, signals read operation ready, leave open when un-
used
P positive power supply
P negative power supply
I/O ROM data bus (lower byte)
P positive power supply
P negative power supply
I/O ROM data bus (higher byte)
P
P
I
I
P
P
positive power supply
negative power supply
DPRAM address bus, range = 2^11 = 2048
DPRAM chip enable, active low
positive power supply
negative power supply
O
O
O
O
O
I
PU
Electrical Specifications
Absolute Maximum Ratings ( Non Operating)
SYMBOL
VDD
V
in
I
in
T
strg
T
sold
t
sold
H
ESD
PARAMETER
DC Supply Voltage
Input Voltage on any Pin
Input Current on any Pin
Storage Temperature
Soldering Temperature
Soldering Time
Humidity
Electrostatic Discharge
5%
1000 V
MIN
-0.3 V
- 0.3 V
-100 mA
-55 oC
MAX
7.0 V
VDD + 0.3 V
100 mA
150 oC
260 oC
10 sec
85 %
NOTE
25°C
1)
Reflow and Wave
HBM: R = 1.5 kΩ , C = 100 pF
1)
300 oC all ceramic packages and DIL plastic packages, 260 oC for surface mounting plastic packages
Note:
Stresses above those listed under “
Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may effect device reliability (e.g. hot carrier degradation).
Rev. NC, October 1999
Page 5 of 13
